1. Field of the Invention
The invention relates in general to a fabrication for semiconductor devices, and more particularly to a method for forming inter-metal dielectric (IMD) layers or interlayer dielectric (ILD) layers.
2. Description of the Related Art
Inter-metal dielectric layers are generally used to separate and electrically isolate wiring lines and other conductors in semiconductor circuit devices. Such devices may include multiple layers of wiring lines and other conductors and require isolation between adjacent conducting structures and isolation between layers. As devices are being scaled down to smaller geometries, the gaps between wiring lines generally have higher aspect ratios (ratio of height to width), which are harder to fill than small aspect ratio gaps. In addition, as the distance between wiring lines and other conductors becomes smaller, capacitive coupling between wiring lines and other conductors becomes a limitation on the speed of the integrated circuit device. For adequate device performance in reduced dimension devices, it is necessary for the dielectric provided between wiring lines to meet a number of requirements. The dielectric material should be able to completely fill the gap between conductors and should be planarizable so that successive layers can be deposited and processed. The dielectric material should also be resistant to moisture transport and have a low dielectric constant to minimize wiring capacitance between conductors and between layers.
It is extremely important to deposit a high quality, substantially void-free dielectric that can fill the small, high-aspect ratio gaps between wiring lines. Dielectric layers for wiring line isolation are often formed by chemical vapor deposition (CVD) processes, which deposit material onto a surface by transporting certain gaseous precursors to the surface and causing the precursors to react at the surface. Common CVD methods include atmospheric-pressure CVD (APCVD), low-pressure CVD (LPCVD) and plasma-enhanced CVD (PECVD). High quality APCVD and LPCVD oxides may be deposited at high temperatures (650-850xc2x0 C.), but such temperatures are generally not compatible with preferred wiring materials such as aluminum or copper. Lower temperature APCVD and LPCVD processes tend to yield oxides that are comparatively more porous and water absorbing and that may be poorly suited to use as inter-metal dielectrics. Acceptable oxides may be formed using PECVD processes, which use a plasma to impart additional energy to the reactant gases. The additional energy supplied by the plasma enables PECVD processes to be carried out at lower temperatures (approximately 400xc2x0 C. and less) than APCVD or LPCVD processes.
As devices are being scaled down to smaller geometries, conventional CVD techniques cannot adequately fill the high aspect ratio gaps between wiring lines (or other conducting structures) on a substrate surface. Conventional techniques such as PECVD tend to deposit material in a manner such that voids become enclosed between the wiring lines. Such voids may be uncovered during subsequent processing and result in contamination that can damage wiring lines or contacts, diminishing device performance.
High density plasma chemical vapor deposition (HDPCVD) allows for the addition of a sputter component to a plasma deposition process which can be controlled to promote gap-filling, during deposition processes in a manner superior to conventional CVD processes. HDPCVD deposits a dielectric layer having superior density, moisture resistance and planarization properties as compared to conventional CVD dielectric layers. The bias sputtering component of HDPCVD derives from the introduction of an accelerating potential between the plasma-excited deposition gases and the deposition substrate. The ions accelerated through the bias sputter component of HDPCVD processes etch the material present on the surface of the deposition substrate and sputter the etched material, generally to further recessed portions on the substrate. As an oxide is deposited onto the surface of a substrate by HDPCVD incorporating bias sputtering, the oxide is also etched from the surface of the substrate and sputtered into recessed portions of the substrate. As such, those portions of a deposited layer that are closest to a gap are the most likely to be etched and sputtered into the gap. This produces the well-known surface faceting of the HDPCVD process and the ability of the process to fill gaps effectively.
HDPCVD processes may accomplish both deposition and etching at the same time, depending on the level of bias sputter component chosen for the deposition environment during the process. Bias sputtering removes and redistributes dielectric material from wiring line sidewalls and enables substantially void-free filling of gaps and enhances planarization. As described above, the sputter component acts to prevent material build-up at the corners of the wiring lines and results in better gap-filling. It should be noted that an excessive etching component during HDPCVD dielectric deposition may damage wiring lines.
It is therefore an object of the invention to provide a method for forming dielectric layers to avoid wiring lines being damaged from the sputtering component of HDPCVD. Wiring lines are formed on a provided semiconductor substrate. Spacers are formed on the sidewalls of the wiring lines. A liner layer is formed on the wiring lines and on the spacers by a first HDPCVD step, such as unbiased unclamped HDPCVD. A dielectric layer is formed on the liner layer to cover the wiring lines and to fill gaps between the wiring lines by a second HDPCVD step.
In the invention, the liner layer is formed by unbiased HDPCVD so that the sputtering component of HDPCVD is removed. The liner layer protects the wiring lines from being damaged. The dielectric layer fills the gaps between the wiring lines without any void and provides a planarized surface.